AMD Takes the Lid off of Next-Gen EPYC 9006 Venice As Zen 6 Comes to Servers

Key Points:

• AMD is preparing to launch the EPYC 9006 series, its largest and most advanced lineup of server CPUs to date, featuring the new Zen 6 architecture and significant upgrades in core count, cache size, and memory support.
• The EPYC 9006 processors will include two chiplet types—high-performance Zen 6 and high-density Zen 6c—both built on TSMC’s 2nm process, with dense configurations reaching up to 256 cores and high-performance chips up to 96 cores.
• A new I/O die in the Venice chips supports up to 16 memory channels, DDR5 RDIMMs at 8000 MT/sec, MRDIMMs up to 12,800 MT/sec, and PCIe Gen6/CXL 3.1, significantly boosting memory bandwidth and I/O capabilities.
• AMD has introduced cache-coherent xGMI interconnects between CPUs and GPUs for the first time, enabling tighter CPU-GPU integration and improved system performance, particularly for AI workloads.
• Power consumption will increase, with the highest-core-count Venice chips reaching up to 600W TDP, reflecting the trade-off for enhanced performance and expanded features in the EPYC 9006 generation.