IBM’s Announces 0.7nm Process Node, Introduces NanoStack

Key Points:

• IBM is advancing semiconductor transistor technology with its new staggered sequential CFET design called NanoStack, promising up to 50% logic area scaling, 50% performance improvement at iso-power, 70% efficiency at iso-performance, and 40% SRAM scaling compared to its own 2nm process.
• Unlike monolithic CFETs, IBM's NanoStack uses sequential wafer bonding with different silicon crystal orientations for NMOS and PMOS transistors, enabling independent optimization and improved transistor performance while addressing thermal and manufacturing challenges with a unique "gate merge" bonding technique.
• The technology aims to achieve a transistor density of approximately 666 million transistors per square millimeter, significantly surpassing current leading process nodes, with expected commercial availability around 2026 and initial adoption likely in smartphones or small AI chiplets.
• IBM is awaiting installation of the High-NA EUV tool at Albany NanoTech to enhance manufacturing efficiency, though the technology can be produced without it through multi-patterning; the new process requires extensive development in EDA tools, thermal management, and defect inspection to support 3D transistor integration.
• While IBM’s NanoStack presents a promising path toward vertical transistor scaling and continued Moore's Law evolution, significant challenges remain in transitioning from research wafers to high-volume production, and broad industry adoption will depend on foundry partnerships and customer willingness to embrace early-stage technology.