AMD's Zen 6 EPYC Venice Pictured as a 256-Core Monster, Massive Twin I/O Dies & First 2nm HPC Chip To Enter Volume Ramp
Wccftech • • technology
Key Points:
- AMD unveiled its next-generation EPYC Venice CPUs at the Advancing AI 2026 event, featuring up to 256 cores based on the new Zen 6 architecture and built on TSMC's cutting-edge 2nm process technology with nanosheet transistors.
- The EPYC Venice chips are designed for high-performance computing workloads, especially Agentic AI and reinforcement learning, offering over 70% improvements in performance and efficiency along with a 30% increase in thread density.
- These CPUs integrate eight massive compute chiplets (CCDs) with 32 cores each and two large I/O dies supporting PCIe 6.0, UCIe, and DDR5 memory, targeting AMD's Helios AI racks for superior throughput and total cost of ownership compared to competitors like NVIDIA's Vera CPUs.
- AMD's 6th Gen EPYC Venice processors mark a significant leap in data center CPU capabilities, leveraging advanced architecture and manufacturing to meet the rising demands of AI-driven workloads, with volume production already underway.
